Semiconductor memory systems employ a plurality of memory cells arranged in columns and rows in accordance with a particular architecture selected. The columns and rows are addressed by means of decoder circuits that can select a particular cell for programming and/or readout. Typically, an integrated circuit (IC) chip will contain the circuit components and the required interconnections. When a large array is located on a chip, it is found that the wiring that interconnects the memory cells involves substantial shunt capacitance. When readout of the memory is accomplished, the sense amplifier will be associated with this shunt capacitance and if voltage readout is accomplished, the capacitance will have to be charged and/or discharged to produce the voltage change to be sensed. It has been found that as array size is increased, the memories are slower to an extent that their performance is compromised. It has also been found that if a current sense amplifier is employed and the voltage changes restricted, the shunt capacitance will not appreciably slow the sensing operation. Therefore, the memory access is substantially speeded up, particularly in large arrays. Clearly any current sense amplifier that acts to restrict the voltage swing will enhance the speed of response.